A frequency domain multichannel access system has been widely used in recent years to satisfy a large number of call requests without failure and to increase the utilization efficiency of frequencies. The multichannel access system is characterized in that a large number of channels are used to construct the system, which is allocated to a large number of subscribers, so that a subscriber may use a vacant channel within the system for his/her call. This system requires a frequency synthesizer which is capable of switching a large number of frequencies easily. It is desirable to reduce the time required for frequency switching in order to realize non-interruption hand-over during the communication.
A frequency synthesizer using a PLL (phase-locked loop) is currently the most prevailing type. A PLL frequency synthesizer phase-locks the output signals from a voltage controlled oscillator (VCO) and the output signals from a reference oscillator. Therefore, if a reference oscillator with a high frequency stability is used, an output with an extremely stable frequency can be obtained in the steady state. The frequency is switched by changing the division ratio, as set at a frequency divider, inside the PLL. The time required for switching frequencies of the PLL frequency synthesizer is determined by the closed-loop bandwidth, which is dependent on the reference frequency, the phase detector gain, etc. Especially when the output frequency spacing has to be set at a narrow value, the closed-loop bandwidth cannot be increased, because the division ratio requires a large value.
Frequency switching of the PLL frequency synthesizer and the conventional method for reducing the time of frequency switching will be described below.
FIG. 1 is a block diagram to show the construction of a conventional PLL frequency synthesizer. The frequency synthesizer comprises a phase detector 1, a variable ratio divider 2, a loop filter 3, and a voltage controlled oscillator 4 (hereinafter referred to as VCO). This circuit forms a phase locked loop or PLL, wherein the output phase of VCO 4 is synchronized with the phase of the reference signal at steady-state. If it is assumed that the frequency of the reference signal is denoted as f.sub.1, the output frequency of VCO 4 as f.sub.0, and the division ratio of the variable ratio divider 2 as N, the output frequency f.sub.0 in the phase locked state can be expressed as the equation (1) EQU f.sub.0 =N*f.sub.1 ( 1)
The output frequency may be switched from f.sub.01 to f.sub.02 by switching the division ratio from N.sub.1 to N.sub.2. If a stable reference signal is supplied, plural stable frequencies may be obtained by switching the division ratio setting at the divider 2. For instance, if the reference signal f.sub.1 is 12.5 kHz, the output frequency may be set stepwise from 1.60 GHz to 1.625 GHz by varying the division ratio N from 128,000 to 130,000.
FIG. 2 shows an example of the transient behavior of the PLL frequency synthesizer during frequency switching. More specifically, when the division ratio set at the divider 2 is switched at the time t.sub.0, the output frequency needs a certain time (time for switching frequency) before it reaches a target frequency f.sub.02. During the transient time, voltage V.sub.c of the capacitor 19 in loop filter 3 in FIG. 1 changes from V.sub.c1 to V.sub.c2 as shown in FIG. 2. The frequency switching time needs to include at least the time necessary for charging and discharging the capacitor. For instance, if it is assumed that the output frequency is in the 1.6 GHZ band and the reference signal frequency is 12.5 kHz, the time required is in the range of 50 ms.
In order to reduce the frequency switching time, there has been proposed a frequency synthesizer having the construction shown in FIG. 3. The construction differs from that of the synthesizer of FIG. 1 in that it is provided with a D/A converter 6 and an adder 5. The adder 5 outputs the sum of the output voltage V.sub.da of the D/A converter 6 and the output from the loop filter 3 as the output for the control or steering voltage V.sub.s of VCO 4. As no electric current passes through the resistors R.sub.1 and R.sub.2 in FIG. 3 in the steady state, the voltage V.sub.c of the capacitor becomes identical to the output from the loop filter 3. Accordingly, the steering voltage V.sub.s of VCO 4 can be expressed by the equation (2) EQU V.sub.s =V.sub.c +V.sub.da ( 2)
It is assumed that the current output frequency is denoted as f.sub.01, and the steering voltage for VCO 4 corresponding thereto as V.sub.s1. If the relation V.sub.da =V.sub.s1 holds, it will hold that V.sub.c =0. If the frequency is to be switched from f.sub.01 to f.sub.02, the division ratio of the variable ratio divider 2 needs to be switched from N.sub.1 to N.sub.2. In the steady state after switching, the VCO controlling voltage corresponding to the frequency f.sub.02 is assumed to be V.sub.s2, and if the relation V.sub.da =V.sub.s2 is set as soon as the division ratio is switched, the relation V.sub.c =0 holds or the voltage of the capacitor stays at 0 volts. This reduces the charging/discharging time of the capacitor in the loop filter. The transient behavior would be the same as that of the construction shown in FIG. 1 if the voltage Vda were unchanged despite the frequency switching. By using the construction of FIG. 3, the time necessary to switch between frequencies is shortened as shown in FIG. 4.
The operation will be further analyzed below. In VCO 4, the relation between the output frequency f and the steering voltage V.sub.s is varied due to changes in temperature, etc. It is assumed that the behavior at the time of frequency switching shows linear voltage controlled characteristics as shown in FIG. 5. The frequency variation of the VCO is extremely small compared to the oscillation frequency, and the frequency drift .DELTA.V.sub.0 could be regarded as constant irrespective of the steering voltage V.sub.s. In FIG. 5, at the time t=t.sub.0, and when the output frequency f.sub.0 is f.sub.01, the steering voltage V.sub.s would be V.sub.s1. When the output frequency of VCO changes by the drift .DELTA.f.sub.0, the steering voltage V.sub.s decreases by the amount of drift compensation voltage .DELTA.V.sub.s by the operation of the PLL so as to maintain the output frequency at f.sub.01. More particularly, the drift compensation voltage -.DELTA.V.sub.c (=- .DELTA.V.sub.s), necessary to compensate the frequency drift .DELTA.f.sub.0 is generated at the capacitor in the loop filter. The output frequency can be quickly switched from f.sub.01 to f.sub.02 by setting a steering voltage V.sub.s2 at the D/A converter disregarding the drift compensation voltage .DELTA.V.sub.c. The VCO steering voltage is set at a value corresponding to a desired frequency (V.sub.s2 -.DELTA.V.sub.s). In this way, the frequency may be switched without changing the voltage at the capacitor.
However, even though the frequency change is maintained constant irrespective of the steering voltage, the relation between the steering voltages of the VCO and the output frequencies f.sub.0 is not absolutely linear, as shown in FIG. 6. For instance, the electrical tuning capacitor C of the VCO may use a varactor diode. In this case, if the drift compensation voltage .DELTA.V.sub.s2 is set as it is, errors will be caused which are equivalent to the difference of the drift compensation voltages .DELTA.V.sub.s1 and .DELTA.V.sub.s2, and the PLL works to charge/discharge the capacitor in order to compensate for the difference. Therefore, the time required for frequency switching is increased.
Moreover, the reference signal phase and the output phase of the variable ratio divider do not always agree immediately after the controlling voltage data is set in the D/A converter. The PLL works to cancel the phase errors to thereby vary the output frequency as shown in FIG. 4.
Because of these reasons, the time required for frequency switching could not heretofore be reduced beyond a certain time.
This invention was conceived to eliminate such problems encountered in the prior art and aims to provide a frequency synthesizer which is capable of high speed switching of oscillation frequency.